1. Technical Field
The present invention relates to forming a contact in semiconductor fabrication, and more specifically, to a method for forming a contact useful for ensuring uniform gate height in replacement metal gate applications.
2. Related Art
During semiconductor fabrication, transistors are formed in a semiconductor substrate. Each transistor includes a gate through which a current can be passed to change the conductivity parameters within the semiconductor substrate. One approach to forming gates includes replacement metal gate (RMG) processing. RMG processing includes generating a number of sacrificial or dummy gates over a structure, such as a fin for a fin field effect transistor (FINFET), so that other processing steps, such as adjacent contact creation, can be carried out without damaging the gate. Once the other processing is carried out, the dummy gates are replaced with a metal to create the final metal gate structure. One challenge of using RMG processing is that it requires the use of multiple chemical-mechanical polishing (CMP) steps. CMP is a method of removing layers of solid by chemical-mechanical polishing carried out for the purpose of surface planarization and definition of metal interconnect patterns.
One challenge related to the CMP during RMG processing is controlling gate height. In one setting, improper gate height can be caused by dishing defects during CMP to expose a top portion of the dummy gates prior to their removal. Dishing defects generally include unwanted removal of portions of material about the dummy gates. Dishing defects can be created by the material being polished being too soft, e.g., poor quality oxide, or the CMP slurry being over-aggressive. Dishing defects can take the form of micro-dishing, which may create concavities within the dummy gate and adjacent spacers due to a high polishing rate of the dummy gate. In this case, deposition of sufficient metal to form the metal gates with the desired height may require additional polishing to remove the concavities and achieve a planar surface. As a result of the additional planarization required, gate height may be lost. Dishing defects can also take the form of macro-dishing, which may occur within the ILD between dummy gates, creating large concavities in the ILD due, for example, to a high polishing rate of the ILD. In this case, deposition of metal, e.g., tungsten (W), to form the metal gates at the desired height also creates metal puddles in the large concavities in the ILD between the gates. As a consequence, additional polishing must be performed to remove the metal puddles, possibly sacrificing gate height in the process.
With further regard to the macro-dishing, the concavities in the ILD may also create issues for processing after the metal deposition to form the metal gates. In particular, after metal deposition, the metal gates may be recessed and the recess filled with a self-aligned contact (SAC) nitride cap for use in creating self-aligned contacts adjacent to the gate to the underlying substrate. Deposition of the SAC nitride cap may also fill any remaining concavity in the ILD, which can create a number of issues. For example, under-polishing after SAC nitride cap formation may leave SAC nitride cap residue on the ILD where the concavity existed that may prevent a subsequent contact open etch reaching the underlying substrate. That is, the SAC nitride cap residue requires a longer etch period, preventing certain locations from opening to the underlying substrate. Alternatively, over-polishing of the SAC nitride cap may not leave enough of the cap to establish isolated contact openings adjacent to the gate. In this case, the contact opening etch may expose a corner of the gate, causing a short of the subsequently formed contact with the gate.